Synchronization and timing are essential to the telecommunications networks to ensure optimal performance and prevent packet loss, dropped frames and degradation of the quality of experience that will affect end-user services. Modern wireless communication systems require at least knowledge of frequency and often knowledge of phase as well in order to work correctly. The communication device such as base station needs to know what time it is, which usually is provided by the network clock synchronization source.
If the connection to the network clock synchronization source is lost (i.e. the network source clock is not available), the base station will have to be on its own to maintain its synchronization clock. The base station needs to find a way to establish accurate frequency and phase (to know what time it is) using internal (or local) resources, and that's where the function of holdover becomes important.
As known in the art, the clock holdover usually refers to an operation condition of a clock which has lost its controlling input, e.g. the network source clock, and is using stored data to control its output. In a typical system, a synchronization module utilizes phase-locked-loop (PLL) circuit to receive the synchronization source and generate one or more high quality clock which is suitable for use. When the synchronization source is lost, the system enters into the holdover mode. In this case, the generated clock will be based on the previously valid synchronization source.
Generally, there are two known circuit designs used for the clock holdover, as illustrated in FIG. 1 and FIG. 2.
In FIG. 1, the first PLL (which is usually an all digital PLL (ADPLL) 1) is connected in series with the second PLL (i.e. the PLL 2). The output signal from ADPLL 1 (marked as “Intermediate Clock”) is supplied as the source clock of PLL 2. Each of the PLLs includes its own independent the phase detector (PD), the loop filter (LP) and the voltage-control oscillator such as the voltage-controlled crystal oscillator (VCXO) and the numerically controlled oscillator (NCO). ADPLL 1 firstly locks to the “External Source Clock”, and generates the “Intermediate Clock”. PLL 2 locks to “Intermediate Clock” and generate one or more “Output Clock” in proper frequencies for the system to use. When both of the PLLs work in the normal locked state, “Intermediate Clock” tracks the frequency of “External Source Clock” and then tracked by “Output Clock”.
When the “External Source Clock” fails, the system enters into the holdover mode. “LF 1” of ADPLL 1 is frozen such that the frequency control word used to drive the NCO to track the change of “External Source Clock” no longer. The frozen output of “LF 1” holds the output of NCO steadily. It is held to a value corresponding to the external source clock received prior to entering the holdover mode.
The topology in FIG. 2 represents a variation of FIG. 1. The difference is that the two PLLs are working in parallel. In the normal operational mode, a selector circuit selects an “External Source Clock” as the input of the PD 2. The “Output Clock” of PLL 2 directly tracks the frequency of the “External Source Clock” and the ADPLL 1 is working in parallel so that it can also track the frequency of the “External Source Clock”. When a holdover condition occurs, the LF 1 is frozen and the selector selects the “Intermediate Clock” as the source clock of the PLL2.
The above clock holdover designs are applicable in the traditional digital telecommunications networks (TDM), where the synchronization was maintained by only two kinds of external source clocks, the primary reference clocks and distribution clocks, over a physical circuit. However, as the networks transit from the TDM networks to packet-based next generation networks, numerous external source clocks with different clock frequencies are presented and the disadvantages of the above designs are exposed.
Specifically, it is known that, for a PLL or ADPLL, the source clock frequency and local oscillator's frequency are preferred to be integral multiples/fraction of each other in the circuit. With the occurrence of the numerous external source clocks with different clock frequencies, it can not be assured that the clock frequency of the local oscillator is always the integral multiply/fraction of the frequency of the different external source clocks. For example, the network clock source may include T-carrier of pseudo-synchronous digital hierarchy (PDH), E-carrier of PDH, synchronous digital hierarchy (SDH)/Synchronous Optical Network (SONET) and SyncE/Global Position System (GPS)/Cesium, whose clock frequency values are 1.544 MHz, 2.048 MHz, multiplies of 6.48 MHz and multiplies of 5 MHz respectively. By contrast, the typical local oscillator includes the VCXO and the oven controlled crystal oscillator (OCXO). The center frequency of VCXO is 155.52 MHz or its integral multiplies, and the output frequency of OCXO is 5 MHz/10 MHz/20 MHz etc.
For both designs in FIG. 1 and FIG. 2, it is common that the “Intermediate Clock” tracks the frequency of “External Source Clock”, such that both the ADPLL1 and the PLL2 are confronted with the issue of the non-integral multiple/non-fraction. Hence it becomes even more difficult for the designer to choose an appropriate frequency of the “Intermediate Clock” which is acceptable by both the ADPLL 1 and PLL 2.
In order to dynamically maintain the integral multiples/fraction relationship between the source clock frequency and local oscillator's frequency for the ADPLL 1 and PLL 2, additional work has to be done on the designs. One approach is to perform the digital non-integral division on the source clock frequency, which however will affect the performance of PD, and an appropriate frequency must be chosen carefully in order to let the PD working well on it. The other approach is to perform the digital non-integral division on the local oscillator's frequency, but it will bring jitter to the PLL's output clock. Furthermore, in order to avoid or alleviate these introduced side-effects, the ADPLL 1 and PLL 2 have to be designed in a more complex way, which in turn increases the circuit manufacture cost.